~~NOTOC~~
======  Minute of meeting on 2020.01.22 ======
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===== 1.  Attendees  =====

  * Alessandro Ferrari ()\\
  * Alex Harding (SEAKR)\\
  * Austin Lesea (Lockheed Martin) \\
  * Brandon Wong ()\\
  * Carl Best (ViaSat)\\
  * Charles ()\\
  * Christian M. Fuchs (Leiden University, Netherlands) \\   
  * Cody Brewer (JSC-NASA)\\
  * Daniel Cochrane ()\\
  * Eliot Glaser (Northrop Grumman) \\ 
  * Gary Swift (meeting moderator, Swift ERS) \\
  * Heather Quinn (LANL)\\
  * Javier Valle (TI, **presenting today**)\\
  * Jeff Dame ()\\
  * Jeff Evers ()\\
  * John J. ()\\
  * Justin Wilhelm ()\\
  * Maggie (Maggie Byers, Raytheon?)\\
  * Matthew Davis ()\\
  * Minal Sawant (Xilinx)
  * R. Pinto (Ricardo Pinto, ESA?)\\
  * Raichelle Aniceto (Facebook)\\
  * Romel Haq (Avnet)\\
  * Ron Smith (Northrop Grumman) \\
  * Scott Doyle (The Aerospace Corporation)\\
  * Sebastian Garcia (Slabs) \\
  * Steve Pearl (General Dynamics)\\
  * Will Rice ()\\
  * (2) unidentified call-in users \\


===== 2.  Topics covered =====

//NOTE: The following are very brief descriptions. Being this a Wiki, please complete/expand/correct them if you think we are missing interesting information (especially regarding anything important for future reference). 
//
//Paragraphs below are comments made by Gary during the call (unless otherwise indicated).//

(NOTE: Raichelle kindly wrote this MoM.)

** Announcements **\\
Boeing is putting finishing touches on DUT and Gen-4 devices to test KU060. No large technical changes from this point. Converged on power planes - Less than 1% voltage drop. Request for XRTC members to review schematics, layout, stack up etc files on swiftradiation.com. 

**Today's presentation**\\
// SEE CHARACTERIZATION OF A 18 A BUCK CONVERTER TO POWER LOW VOLTAGE, HIGH CURRENT SPACE FPGAS, //
Javier Valle (TI Space Power Products Systems Manager).
Reference recording for slides and comments. Slides to be posted to wiki.
  * Background
    * TPS7H4001-SP: 3-7 Vin, 18A, current mode monolithic QMLV POL DC-DC Converter
    * BiCMOS Process
    * Developed in rad hard process: TID 100 krad, SET/SEFI characterized, SEL/SEB/SEGR immune up to 75 MeV.cm2/mg
    * Low Voltage Internal Reference of 0.6V
  * Application: Satellite power management and distribution
  * Benefits:
    * Higher output current in smaller footprint for powering high current FPGA and ASIC core voltage rails
    * Ease of implementing sequencing schemes
    * Easy parallel operation of up to 4 of these devices for higher devices without need for external clock 
    * Defined, designed, developed and fully characterized at 18A for space FPGA applications (no SEFI, very low SET cross section)
  * TAMU SEE Campaigns
    * No destructive SEEs observed
    * Second and final silicon revision SEFI free. 
    * No SEL/SEB/SEGR observed. 
    * Qty. 10 SETs with < 3% from nominal voltage observed. No SETs with > 3% from nominal voltage observed. 
  * SEE Rate Calcs
    * Comment (Gary Swift): Approach in rate calcs - Assuming Onset LET 75 with saturated cross section – evaluating as a step function with everything below LET 75 as “0” and then above 75 as saturated cross section. MTBE and rate may be higher than calculated if calculate rates with data above LET 75. 
    * Response: TI does not test above LET 75. Rate calcs for SET < 3% from nominal voltage still to be released. Dilemma between good statistics vs. engineering “good enough” 


